The present invention is in the field of microwave field effect transistors, and more specifically, is in the field of microwave power devices and integrated circuits that combines a lateral LDMOS structure to a composite material substrate technology.
In the prior art, power high frequency devices have been built using a variety of semiconductor technologies. For a long time the preferred vehicle for their realization has been the NPN bipolar junction transistor (BJT). Its primary advantage was the achievable high intrinsic transconductance (gm) that permitted the fabrication of high power devices utilizing small silicon areas.
As processing technology improved, in the early 1970""s a number of MOSFET vertical structures begun to challenge the dominance of the BJT at the lower RF frequencies, trading the cost of the large silicon area, necessary to provide the current capability in MOSFETs, for the cost of simple processing. The advantages that the MOSFET structure provided to the user were: higher power gain, ruggedness (defined as the capacity to withstand transients) and ease of biasing.
In the mid 1990""s, new RF MOS devices that utilize the standard lateral MOS structure with a connection to the backside of the chip such that the back side becomes electrical and thermal ground, have extended the operational advantage of the MOSFET over the BJT into the 3 GHZ region thus covering three commercial bands of great importance: the cellular, PCS/PCN, and 3 G mobile telephone bands.
This concept of using the back side of the chip as an electrical and thermal ground was disclosed in the U.S. Pat. No. 5,949,104, issued to XEMOD, Inc.
In order to surmount the 3 GHz barrier, microwave power FET devices have been fabricated in a number of material combinations of active layers and substrates (besides Silicon) in order to obtain advantages in electrical performance. Gallium Arsenide (GaAs) was the first compound material investigated to fabricate devices at microwave frequencies (defined as those above 3 GHz). Also, lately Gallium Nitride (GaN) and even Silicon Carbide (SiC) have been tested as possible substitute materials on which to fabricate high performance microwave FET power devices.
Notwithstanding this onslaught of activity in these exotic materials, Silicon remains the material of choice for the fastest, high volume production of FET devices in the world. In fact, the question now is not how to obtain higher electrical performance out of Silicon FETs but since tighter and smaller geometries are being used to improve speeds of operation, the limitation that these devices built in Silicon experience is thermal dissipation.
Attempts to remove the thermal constraint have been made with SiC, a material that, on paper, has excellent electrical and thermal characteristics. Unfortunately, these efforts to utilize SiC material in the fabrication of devices for microwave power devices are hindered by technological problems associated with crystal growth, purity and doping; plus problems related to the development of suitable ohmic contacts and rectifying junctions. Although rapid progress has been made recently in all these areas, growth and device fabrication technology is still primitive as compared to that of Silicon devices. Presently the only SiC devices commercially available, fabricated in volume, are high power, high voltage diodes.
Temperature has a significant effect on operation of SiC devices. The free loci electron density in the active region of the material depends on the dopant density and it""s activation energy. Unfortunately, the most commonly used dopants in Silicon Carbide require high activation energies as compared to Silicon and therefore for a given level of dopant, SiC has considerable less free electrons available and/or higher charge scattering, that is more resistivity. This is also true for P-doped layers.
Thus, for the time being, the Silicon Carbide (SiC) material is the best one suited to be used as a semiconductor active layer for high temperature applications ( greater than 250xc2x0 C.) whereas all the donor and acceptor charges get fully activated. However, one of the characteristics of SiC, namely high thermal conductivity, could be utilized advantageously in the development of hybrid Silicon Carbide based active and passive structures.
This new concept was described in the assigned to the assignee of the present patent application U.S. patent application Ser. No. 10/078,588, filed on Feb. 14, 2002, and entitled xe2x80x9cHIGH PERFORMANCE ACTIVE AND PASSIVE STRUCTURES BASED ON SILICON MATERIAL GROWN EPITAXIALLY OR BONDED TO SILICON CARBIDE SUBSTRATExe2x80x9d, that is hereafter referred to as the patent application #1. The patent application #1 is incorporated in the present patent application in its entirety. The technology described in the patent application #1 is designated herein as the Si2C technology.
As the applications for wireless communications move up in the frequency spectrum, parasitic resistances, capacitances and inductances limit the performance of the multiple conductive plug structure for lateral RF MOS devices, as described in the ""104 patent.
What is needed is a new microwave transistor structure that includes a lateral LDMOS plug structure, as described in the ""104 patent, that includes a SiC substrate, as disclosed in the patent application #1, and that has an improved performance due to reduced parasitic capacitances.
To address the shortcomings of the available art, the present invention provides a new microwave transistor structure built on SiC substrate, and that advances the frequency capabilities of the microwave transistor structure by diminishing the gate-to-drain Cgd capacitance, without impacting, in a deleterious manner, the other inter-electrode capacitances, including the gate-to-source Cgs capacitance.
One aspect of the present invention is directed to a microwave transistor structure comprising: (a) a SiC substrate having a top surface; (b) a silicon semiconductor material of a first conductivity type including a first dopant concentration; the silicon semiconductor material is overlaying the top surface of the semiconductor substrate and has a top surface; (c) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (d) a channel region of the first conductivity type formed completely within the silicon semiconductor material including a channel dopant concentration; (e) a drain region of the second conductivity type formed in the silicon semiconductor material and contacting the channel region; (f) a body region of the first conductivity type and having a body region dopant concentration formed in the silicon semiconductor material under the conductive gate region, any remaining portion of the silicon semiconductor material underlying the gate is of the first conductivity type; (g) a source region of the second conductivity type and having a source region dopant concentration formed in the silicon semiconductor material within the body region; (h) a shield plate region being adjacent and being parallel to the drain region formed on the top surface of the silicon semiconductor material over a portion of the channel region; the shield plate region is adjacent and parallel to the conductive gate; the shield plate extends above the top surface of the silicon semiconductor material to a shield plate height level, and is insulated from the top surface of the silicon semiconductor material; and (i) a conductive plug region formed in the body region of the silicon semiconductor material to connect a lateral surface of the body region to the top surface of the substrate.
In one embodiment, the silicon carbide substrate further comprises a substantially heavily doped silicon carbide substrate providing a thermal path and an electrical path for the microwave transistor. In another embodiment, the silicon carbide substrate further comprises a substantially lightly doped silicon carbide substrate having a substantially high resistivity and providing a thermal path for the microwave transistor.
In one embodiment of the present invention, the drain has a drain dopant concentration greater than the channel region dopant concentration. In one embodiment of the present invention, the body region dopant concentration is equal or greater than the first dopant concentration.
In one embodiment of the present invention, the channel region (d) further includes: (d1) a first enhanced drain drift region of the first conductivity type and having a first enhanced drain drift region dopant concentration; and (d2) a second enhanced drain drift region of the second conductivity type and having a second enhanced drain drift dopant concentration contacting the first drain drift region.
In one embodiment, the second enhanced drain drift dopant concentration is greater than the first enhanced drain drift region dopant concentration; and the drain region dopant concentration is greater than the second enhanced drain region dopant concentration.
In one embodiment, the microwave transistor structure of the present invention further includes a contact enhanced region of the first conductivity type located within the body region and having a contact enhanced region dopant concentration. In one embodiment, the contact enhanced region dopant concentration is greater than the body region dopant concentration.
In one embodiment, the conductive plug region further includes a conductive plug region formed in the contact enhanced region and the body region and connecting a top surface or a lateral surface of the contact enhanced region and a lateral surface of the body region to the top surface of the substrate. The conductive plug further comprises a metal plug, or a silicided plug. The silicided plug is selected from the group consisting of a tungsten silicided plug, a titanium silicided plug, a cobalt silicided plug, and a platinum silicided plug.
In one embodiment, the conductive gate further comprises a highly doped polysilicon gate. In another embodiment, the conductive gate further comprises a sandwich gate further comprising a highly doped polysilicon bottom layer and a top layer selected from the group consisting of a tungsten silicided, a titanium silicided, a cobalt silicided, and a platinum silicided.
In one embodiment, the shield plate region further includes a shield plate region connected to the source region. In an alternative embodiment of the present invention, the shield plate region further includes a shield plate region connected to a backside of the structure. The shield plate further comprises: a metal shield plate; or a polysilicon shield plate; or a polysilicon/silicided shield plate sandwich; or a polysilicon/metal shield plate sandwich.
Another aspect of the present invention is directed to a microwave transistor structure comprising: (a) a SiC substrate having a top surface; (b) a bonding layer overlying the SiC substrate; (c) a silicon semiconductor material having a top surface and overlaying the bonding layer; wherein the silicon semiconductor material is bonded to the SiC substrate via the bonding layer; (d) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (e) a channel region of the first conductivity type formed completely within the silicon semiconductor material including a channel dopant concentration; (f) a drain region of the second conductivity type formed in the silicon semiconductor material and contacting the channel region; (g) a body region of the first conductivity type and having a body region dopant concentration formed in the silicon semiconductor material under the conductive gate region, any remaining portion of the silicon semiconductor material underlying the gate is of the first conductivity type; (h) a source region of the second conductivity type and having a source region dopant concentration formed in the silicon semiconductor material within the body region; (i) a shield plate region being adjacent and being parallel to the drain region formed on the top surface of the silicon semiconductor material over a portion of the channel region; the shield plate region is adjacent and parallel to the conductive gate; the shield plate extends above the top surface of the silicon semiconductor material to a shield plate height level, and is insulated from the top surface of the silicon semiconductor material; and (k) a conductive plug region formed in the body region of the silicon semiconductor material to connect a lateral surface of the body region to the top surface of the substrate.
The bonding layer comprises: a carbon layer; or a silicon layer; or a silicon dioxide layer; or a metal silicided layer selected from the group consisting of: a tungsten silicided layer, a titanium silicided layer, and a cobalt silicided layer.
One more aspect of the present invention is directed to a microwave transistor structure comprising: (a) a SiC substrate having a top surface; (b) a first silicon dioxide layer overlaying the SiC substrate; (c) a second silicon dioxide layer; (d) a silicon semiconductor material of a first conductivity type having a first dopant concentration, a top surface, and a bottom surface; wherein the bottom surface of the silicon semiconductor material is overlaying the second silicon dioxide layer; and wherein the silicon semiconductor material is bonded to the SiC substrate via the first silicon dioxide layer and via the second silicon dioxide layer; (e) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (f) a channel region of the first conductivity type formed completely within the silicon semiconductor material including a channel dopant concentration; (g) a drain region of the second conductivity type formed in the silicon semiconductor material and contacting the channel region; (h) a body region of the first conductivity type and having a body region dopant concentration formed in the silicon semiconductor material under the conductive gate region, any remaining portion of the silicon semiconductor material underlying the gate is of the first conductivity type; (i) a source region of the second conductivity type and having a source region dopant concentration formed in the silicon semiconductor material within the body region; (k) a shield plate region being adjacent and being parallel to the drain region formed on the top surface of the silicon semiconductor material over a portion of the channel region; the shield plate region is adjacent and parallel to the conductive gate; the shield plate extends above the top surface of the silicon semiconductor material to a shield plate height level, and is insulated from the top surface of the silicon semiconductor material; and (l) a conductive plug region formed in the body region of the silicon semiconductor material to connect a lateral surface of the body region to the top surface of the substrate.